This invention relates to matrix addressable displays. Matrix addressable displays comprising a two dimensional array of switchable cells are known, in which each cell has two electrodes each carried on a surface of a respective one of two plates. Each cell is switchable by means of electric signals applied to a respective pair of address lines connected to the cell. Each of the address lines of a pair is connected to a different plurality of cells within the array.
To overcome the problems of multiplexing the address lines in such a display, i.e. in order to identify uniquely the cell to be switched at any one time and to prevent partial switching of other cells connected to one of the pair of address lines, it is known to connect each cell to its respective pair of address lines via a respective transistor, for example a thin film transistor, i.e. the so-called `active matrix addressing` approach.
FIG. 1 is a schematic circuit diagram of part of such a known display.
Referring to FIG. 1, the illustrated part of the display comprises an array of liquid crystal cells C11 to C22, each cell being represented in the figure as a capacitor. One electrode 3 of each cell is carried on the inner surface of a transparent first insulating plate, the electrode 3 being the size of a pixel of the display, and being made of a transparent conductor such as indium tin oxide. The other electrode 5 of each cell is defined on the opposing surface of a second insulating plate, this surface carrying a series of parallel conductive column tracks 7, 9, 11. All components carried on this second plate are shown dotted in the figure.
In respect of each cell, there is provided a respective thin film field effect transistor T11 to T22 carried on the first plate. One main electrode of each transistor, hereinafter referred to as a drain for convenience, is connected to the electrode 3 of each cell, whilst the gate of each transistor is connected to a selected gate address line 13, 15, 17 within a series of parallel conductive row tracks on the first plate. The second main electrode of the transistor, hereinafter referred to as the source for convenience, is connected to a reference line which is one of a group of conductive row tracks 19, 21 extending across the first plate parallel to the gate address lines 13, 15, 17. The reference lines may be earthed.
There has been a proposal to combine adjacent reference and gate lines, such as the lines 19 and 15, into a single line, thereby simplifying the manufacturing processes.
In the use of the display, appropriate synchronised gate and source voltage pulses are applied to a selected pair of gate and column address lines. This then selectively addresses the one transistor which is connected to both the selected address lines. The capacitor constituted by the cell connected to the selected transistor is then able to charge up to the voltage required to give a response in the liquid crystal cell. The capacitor is then isolated when the transistor is subsequently switched off, and the charge held on the capacitor is effective to switch the cell in the sense of changing the transmittance of the liquid crystal and thus producing the required pixel image.
However, such a display suffers from the disadvantage that a single-short circuit in a transistor gate results in the failure of the entire row of the display to which the shorted transistor belongs. Even a single row failure is totally unacceptable in a display. Such row failures could be turned into single pixel failures by identifying and disconnecting faulty transistors, single pixel failures being much less noticeable and therefore being tolerable in some applications. This process is, however, time-consuming and expensive, particularly for large numbers of pixels.
In order to overcome this problem, it has been proposed to insert a high-value resistance element in the connection between each transistor and the respective row track, such as indicated by a resistor 23 shown in dotted outline in FIG. 1. However, no indication has previously been given as to how such a resistor is to be formed in a practicable manufacturing process.